This disclosure relates to data processing.
Data processing arrangements can make use of pipelined decoding and execution of instructions. The decoding process involves, as part of its functionality, allocating processor resources to the decoded instructions. The processor resources may be, for example, processor registers or register mappings and/or entries in buffers or the like such as re-order buffers, renaming lists or reservation stations.
If, at decoding, insufficient processor resources are available, the decoding of an instruction is stalled and may be cancelled. But the determination of resource availability cannot be made until late in the decoding cycle.